STARTUP
Oscillators do not become valid at the instant power exists.
Crystals, ceramic resonators, RC oscillators, MEMS oscillators, and external clock sources have startup behavior. Supply ramp, drive level, load capacitance, temperature, component tolerance, and board contamination can affect whether and how quickly oscillation reaches a usable amplitude and frequency.
Firmware that switches immediately to an external oscillator because “it should be there” can fail intermittently on cold start while working perfectly after a warm reset. Use hardware ready flags or measured startup criteria where available and define a timeout/fallback policy.
PLL LOCK
A configured PLL is not necessarily a locked PLL.
Phase-locked loops multiply or otherwise synthesize clock frequencies from a reference. They need time to settle, and they operate only within specified input and output ranges. Changing dividers, source clocks, or supply conditions can temporarily make the output invalid.
Switch critical domains only after the PLL reports lock under the device's prescribed sequence. If lock is lost during operation, know which clocks remain valid and whether the system can fall back safely instead of continuing on a broken assumption.
TOLERANCE
Nominal frequency is not actual frequency.
Clock sources have initial tolerance, temperature coefficient, aging, supply sensitivity, and sometimes load-capacitance sensitivity. Two devices nominally running at the same frequency can differ enough to consume communication timing margin.
Asynchronous serial protocols tolerate only a finite transmitter/receiver frequency mismatch before sample points drift too far within a frame. CAN timing similarly depends on oscillator tolerance, propagation delay, and resynchronization. A network that works at room temperature can become marginal at environmental extremes.
CLOCK TREE
One root clock becomes many derived assumptions.
Microcontrollers route clocks through muxes, prescalers, PLLs, peripheral gates, and bus domains. Changing one divider can alter timer rate, baud generation, ADC clock, watchdog behavior, USB timing, and kernel scheduling.
Document the tree in physical units, not only register values. “APB prescaler = 2” is less useful than “timer kernel = 100 MHz under this mode.” When dynamic power modes switch trees, log the active source and divider state alongside failures.
TIMERS
Some timers secretly run at a different rate than their bus.
Many MCU families contain timer-specific multiplier behavior, independent low-speed oscillators, or peripheral clock selections that differ from the core clock. Assumptions copied from one timer to another can create silent frequency errors.
Measure a timer output on a pin when timing matters. A square wave turns three pages of clock-tree interpretation into one oscilloscope measurement.
SWITCHING
Changing clock source is an operating transition.
Dynamic frequency scaling and low-power modes can switch between oscillators or alter PLL/divider settings. Peripherals active during the transition may see stretched, shortened, or paused timing depending on architecture.
Sequence changes according to the device reference manual. Quiesce sensitive peripherals when required. Recalculate software timing constants or configure them from actual clock state rather than compile-time mythology.
ASYNC BOUNDARIES
Clock-domain crossings are not solved by hoping both domains are fast.
Signals crossing asynchronous clock domains can violate setup/hold timing and produce metastability. Single-bit controls often need synchronizers. Multi-bit values need handshakes, asynchronous FIFOs, Gray-coded counters, or other structures that preserve coherence across domains.
This problem exists in FPGAs and ASICs visibly, but related boundaries also appear between MCU peripherals, external devices, DMA engines, radios, and independently clocked sensor interfaces.
MEASUREMENT
Measure the clock instead of inferring it from code.
Route internal clocks to a clock-output pin where supported. Toggle a GPIO from a timer. Measure peripheral baud or bus period. Observe crystal pins only with appropriate probes because probe capacitance can disturb the oscillator you are trying to diagnose.
Frequency counters and oscilloscopes answer different questions. A counter gives excellent average frequency. A scope exposes startup, jitter, missing cycles, duty cycle, and switching transients.
TEMPERATURE
Timing margin can be environmental margin.
Clock drift with temperature can push baud mismatch, PLL acquisition, RF frequency error, or timer accuracy across a threshold. If a protocol failure correlates strongly with cold start or enclosure temperature, put clock accuracy on the suspect list before rewriting the driver.
For precision timing, use the clock technology and compensation strategy that match the requirement: calibrated RC, crystal, TCXO, disciplined oscillator, network synchronization, GPS, or another reference.
FIELD METHOD
Debug timing from the root outward.
1. Inventory every clock source. Record nominal frequency, tolerance, startup behavior, and dependent domains.
2. Confirm ready/lock state. Preserve failures rather than silently retrying forever.
3. Output measurable clocks. Verify actual frequency in each power/performance mode.
4. Test temperature and supply variation.
5. Correlate protocol errors with clock transitions.
6. Inspect asynchronous boundaries. Repeated single-bit corruption is not always software race.
7. Recalculate timing after clock-tree changes. One prescaler edit can invalidate several peripherals at once.
BOTTOM LINE
Every timing error has a clock somewhere in its ancestry.
Clock trees are shared infrastructure. When several unrelated peripherals become unreliable together, the common clock source, PLL, divider, power mode, or synchronization boundary deserves suspicion.
Before debugging five protocols, verify the one clock tree they all inherited.
SOURCE TRAIL
Technical starting points.
STMicroelectronics AN2867 — oscillator design guide
NXP — crystal oscillator design considerations