FOUR MODES
CPOL and CPHA decide which edges mean what.
SPI devices commonly describe four clock modes from clock polarity and clock phase. Polarity determines the idle clock level. Phase determines which transition is used to sample versus shift data.
A mode mismatch can produce data that is completely wrong, consistently shifted, or maddeningly intermittent depending on setup/hold margin and clock speed. If communication only works at very low frequency, verify mode before inventing a signal-integrity theory.
CHIP SELECT
The transaction often starts before the first clock edge.
Peripheral datasheets specify setup time from chip-select assertion to the first active clock, hold time after the last clock, and sometimes a minimum inactive time between transactions. Some devices use chip select to reset an internal bit counter or commit a command. Others permit it to remain asserted across multiple words. These behaviors are not interchangeable.
A controller peripheral that automatically toggles chip select between words can break a device that expects one continuous frame. Firmware that holds chip select forever can break a device that requires an inactive edge to finish the command.
MISO
A shared return line only works if inactive devices truly let go.
Multiple SPI peripherals can share MOSI, MISO, and SCLK when each has an independent chip-select line and inactive devices place their MISO output in high impedance. If a peripheral drives MISO while not selected, two outputs can contend electrically.
Some devices power up in unusual pin modes. Some require configuration before tri-stating correctly. Partial power can create back-power or clamp paths. If the bus fails only when one additional peripheral is connected, scope MISO with chip selects visible rather than blaming software order.
FULL DUPLEX
Every transmitted bit clocks a received bit, whether you wanted one or not.
SPI shifts in both directions simultaneously. Commands that appear conceptually “write then read” may actually require dummy bytes while the peripheral prepares and returns data. The first received bytes can be meaningless command-phase residue; the meaningful response may begin later.
Drivers should encode transaction phases explicitly rather than assuming the receive buffer lines up with application fields because both happen to be the same length.
WORD SIZE
Eight bits is common, not universal.
Devices may use 8-, 16-, 24-, or other-width transfers, and byte order within a multibyte register can differ from processor endianness. Some controllers insert gaps between hardware words even while chip select remains low. A peripheral may interpret that gap as irrelevant or as a violation.
When moving from polling code to DMA, verify that the DMA/controller combination preserves the exact on-wire frame the device expects.
DMA
A faster transfer engine can change transaction boundaries.
DMA is excellent for reducing CPU load and jitter, but it also separates buffer completion from physical wire completion. A DMA interrupt may fire when the last byte has entered the SPI peripheral, while the shift register is still transmitting.
If firmware deasserts chip select immediately on DMA completion, the final bits can be truncated. The correct completion condition is implementation-specific and often includes waiting for the SPI peripheral's busy flag or transfer-complete condition, not merely DMA completion.
EDGE RATE
The clock frequency is not the fastest thing on the wire.
Signal-integrity problems are driven strongly by rise and fall time, interconnect geometry, impedance discontinuities, and return path. A 2 MHz SPI clock generated by a modern GPIO can still have nanosecond edges capable of ringing badly on a long cable or poorly routed board.
Series damping near the source, continuous return paths, shorter stubs, and lower drive strength can sometimes improve the waveform more effectively than simply reducing nominal clock frequency.
NO ACK
Silence can look exactly like success.
Basic SPI provides no universal acknowledgement that a peripheral existed, understood the command, or accepted the write. A disconnected sensor may return all ones or all zeros depending on pull state and input bias. Those values can look legitimate if software fails to apply plausibility checks.
Use device identity registers, status bits, CRCs where supported, command-response invariants, or higher-level reasonableness checks. “The transfer completed” usually means the controller generated clocks. It does not mean the peripheral agreed with reality.
FIELD METHOD
Put transaction framing on the scope.
1. Capture SCLK, chip select, MOSI, and MISO together. Decode is useful only after the physical frame is visible.
2. Verify CPOL/CPHA against the peripheral datasheet.
3. Measure chip-select setup, hold, and inactive time.
4. Compare polling and DMA waveforms. Do not assume optimization preserved framing.
5. Inspect MISO while each device is deselected. Find contention and partial-power behavior.
6. Slow the clock and soften edge rate separately. They diagnose different problems.
7. Add semantic validation. Identity, CRC, status, and range checks make a mute peripheral harder to mistake for a successful exchange.
BOTTOM LINE
SPI is simple because it delegates discipline to the designer.
There is little protocol machinery to rescue you from a bad transaction boundary. That is why chip-select timing, device-specific framing, physical edge quality, and higher-level response validation deserve explicit treatment.
The controller can finish a transfer perfectly while the peripheral participates in a different conversation.
SOURCE TRAIL
Technical starting points.
Microchip — SPI peripheral documentation
Analog Devices — Introduction to SPI Interface