Sensor plausibility needs physics
Range checks, rate limits, cross-sensor constraints, stuck values, impossible combinations, and fault detection that knows something about the machine.
ELECTRONICS + EMBEDDED SYSTEMS / ACTIVE DEPARTMENT
Power rails, return paths, electromagnetic coupling, analog measurement, clocks, buses, radios, reset behavior, firmware updates, nonvolatile state, thermal limits, and the hardware-software boundary where “random” failures usually turn out to be deterministic once the right signals are measured.
POWER + SIGNAL INTEGRITY
Rail impedance, return geometry, edge rate, thermal behavior, source transitions, and external cables all become part of the machine once current starts moving through real copper.
Undervoltage, supervisors, sequencing, interrupted writes, load transients, reset evidence, and partial-power recovery.
Read → 002 / RETURN CURRENTShared impedance, ground bounce, mixed-signal layout, decoupling, cable references, and measurement loops.
Read → 003 / EMCConducted, capacitive, inductive, common-mode, and radiated paths plus practical source-path-victim diagnosis.
Read → 008 / THERMAL CONTROLJunction temperature, derating, thermal inertia, sensor placement, throttling, cooling failures, and deliberate capability reduction.
Read → 011 / POWER PATHSSource priority, ideal diodes, charging while operating, inrush, reverse current, USB transitions, and switchover brownouts.
Read →BUS + TIMING SYSTEMS
I²C, CAN, SPI, and the clocks underneath them fail differently. The common mistake is believing a completed controller transaction proves that the peer, physical layer, and application all agreed.
Pull-ups, capacitance, rise time, stuck buses, clock stretching, partial power, level shifting, and bounded recovery.
Read → 006 / CANTermination, topology, arbitration, error counters, bus-off, common-mode limits, transceiver state, and timing.
Read → 009 / SPICPOL/CPHA, chip-select setup/hold, MISO contention, DMA completion, edge rate, transaction framing, and response validation.
Read → 014 / CLOCK TREEOscillator startup, PLL lock, tolerance, temperature drift, clock switching, asynchronous boundaries, and inherited peripheral timing.
Read →FIRMWARE + PERSISTENT STATE
Boot, update, storage, watchdogs, and diagnostics form one survivability problem. A device should fail during update or runtime, recover coherent state, and leave enough evidence to explain what happened.
Progress monitoring, windowed watchdogs, reset scope, evidence preservation, idempotent startup, and repeated-reset escalation.
Read → 007 / BOOT + UPDATESigned images, A/B slots, interrupted updates, provisional boots, rollback, migration, downgrade policy, and recovery channels.
Read → 010 / NONVOLATILE STATEErase granularity, endurance, hot variables, wear leveling, journals, power-fail atomicity, and generation counters.
Read → 012 / DIAGNOSTICSReset cause, crash signatures, retained memory, boot attempts, progress markers, watchdog ownership, image state, and clock basis.
Read →MEASUREMENT + RADIO
Converters and radios are instruments. Resolution, received power, and register outputs only become useful after reference quality, noise, geometry, timing, interference, and application requirements are included.
Reference noise, source impedance, acquisition time, grounding, protection, ENOB, oversampling, calibration, and error budgets.
Read → 015 / RF SYSTEMSLink budgets, fading, interference, retries, antenna detuning, congestion, latency, energy cost, and deliberate degraded modes.
Read → ROBOTICS / SENSOR FUSIONTiming, correlation, bias, covariance, observability, fault detection, and confidence.
Read →TEST + CROSSOVER
The lab should deliberately create the failure states the architecture claims to survive, then measure detection, containment, degraded capability, evidence, and recovery.
Power cuts, stuck buses, biased sensors, corrupt storage, cooling loss, network impairment, bad firmware, pass criteria, and reproducible fault campaigns.
Read → ROBOTICS / TIMINGSampling, transport, estimator age, jitter, filtering, and actuator lag as control constraints.
Read → SOFTWARE / FIRMWAREAcquisition, immutable originals, hashing, containers, embedded filesystems, architecture clues, signatures, and safe lab handling.
Read → ENGINEERING / RESILIENCEFault detection, isolation, reduced capability, common-mode failure, recovery, and operator visibility.
Read →OPEN QUEUE
Range checks, rate limits, cross-sensor constraints, stuck values, impossible combinations, and fault detection that knows something about the machine.
Stall detection, winding resistance, commutation, current control, thermal state, friction, load estimation, and how current becomes both command and diagnostic signal.
Serial numbers, firmware versions, calibration records, measured limits, fixtures, test software, failed units, and the difference between pass/fail and useful manufacturing data.
Contact resistance, fretting, strain relief, ingress, vibration, insertion cycles, intermittent opens, and connectors as one of the least glamorous ways to lose an entire machine.
DEPARTMENT RULE
Intermittent embedded failures still have state, timing, energy, geometry, and causality. Instrument the rails, preserve reset reasons, timestamp the buses, follow return current, and make the failure leave enough evidence to stop being mysterious.